### Overview of current control techniques for single L filter grid-tied inverters

The current control block diagram of the single-L filter grid-connected inverter is shown in Figure 1. The inverter bridge is simply equivalent to a proportional link with a gain of kPWM, and kPWM is the ratio of the DC side voltage to the amplitude of the triangular carrier. However, digital control technology is currently widely used in grid-connected inverters, and the sampling and calculation delays in digital control need to be considered when analyzing and designing closed-loop systems. When using digital control technology, there is a certain delay between current sampling and modulating wave loading. The grid-connected inverter grid-connected current control block diagram that takes into account the digital control delay is shown in Figure 2. The PWM inverter link is replaced by a zero-order keeper (ZOH) to more accurately reflect the delay in current control, and Gc(s) is the current regulator.

### Stability of current control

For current control, the first consideration is its stability. When the control delay is not considered, the open-loop transfer function of the system shown in Figure 1 is

Taking Gc(s) as an example of a PI regulator, its phase is always between -90° and 0°, while the phase of 1/Ls is always -90°. Therefore, the phase of the open-loop transfer function shown in equation (1.1) is always between -180° and 0°. Therefore, according to the logarithmic frequency stability criterion, the system is always stable. Figure 3 shows the open-loop Bode plots before and after the PI regulator compensation, where L=2mH, fs=15kHz, and the PI regulator is 15+15000/s. Since the phase-frequency curve does not cross the -180° phase line, the proportional gain of the PI regulator can be varied in a wide range.

Taking into account the digital control delay, the open-loop transfer function of the system shown in Figure 2 is

Figure 4 shows the open-loop Bode plots before and after current regulator compensation when the digital control delay (Td=Ts) is taken into account. Compared to Figure 3, it can be seen from the dashed-dotted line in Figure 4 that the digitally controlled delay results in a significant reduction in phase and crosses the phase curve through -180°. In this case, the additional current regulator must ensure that the -180° phase crossover frequency is greater than the 0dB amplitude crossover frequency, otherwise the closed-loop system is unstable. As shown by the solid line in Figure 4, when using the same PI regulator as in Figure 3, although the system is still stable, the small phase and amplitude margin means that the system has large overshoot and severe oscillation during the transient adjustment process. For this reason, it is necessary to design the PI regulator parameters reasonably. First, within the system bandwidth, equation (1.2) can be simplified as

The amplitude and phase-frequency relationship of the open-loop transfer function are

The integral link in the PI regulator mainly affects the amplitude and phase characteristics of the low frequency band. When the PI regulator is higher than the corner frequency, the PI regulator can be regarded as a P regulator. That is, when calculating the open-loop cutoff frequency and the crossover frequency, the amplitude and phase of Gc(s) are regarded as kp and 0° respectively.

Let the amplitude of the open-loop transfer function be 1, the open-loop cut-off frequency fc can be obtained as

Substituting the cutoff frequency into equation (1.5), the expression of phase margin PM can be obtained as

Let the phase of the open-loop transfer function equal to -Π, the open-loop crossover frequency fn can be obtained as

Substituting the crossover frequency into Equation (1.4), the expression of the amplitude margin GM can be obtained as

Furthermore, according to equations (1.6) to (1.9) and the expected bandwidth and stability margin, the required regulator parameter kp can be selected. The selection of the integral coefficient mainly considers reducing the steady-state error. After the initial selection of parameters is completed, the final calibration can be carried out.