Time domain analysis of capacitor voltage self-balance mechanism Part 2
This article analyzes the characteristics of the current ix(t) and its average value Ix(avg) from the midpoint of the capacitor arm when Vd=0 and Vd≠0. (1) Vd=0 Vd=0 means that the capacitor voltage is balanced. At this time, iinv(t) is denoted as iinv_b(t), and its expression is: Among them, φZmn is the impedance angle of Zeq, and […]
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