#### Time domain analysis of capacitor voltage self-balance mechanism Part 1

The self-balancing characteristics of the half-bridge inverter can also be analyzed in the time domain. First, analyze the time constant τ of the capacitor voltage stability in the time domain, so as to qualitatively understand the self-balancing characteristics of the capacitor voltage; then, according to the two-variable Fourier decomposition, the factors of the capacitor voltage balance are deduced from the time domain perspective.

First analyze the stable time constant τ of the capacitor voltage. The process of capacitance differential stabilization is a dynamic process. Due to the large capacitance value, compared with the dynamic change of the circuit, the change of the capacitance voltage difference is slow, that is, the difference ix of the current flowing through the capacitance is basically a direct current. In combination with Figure 1, there are: (1) The DC input voltage Udc/2 remains constant during the change of the capacitor voltage difference, so that it has no effect on the time constant for solving the capacitor voltage difference balance. Udc/2 can be seen as 0; (2) The capacitor can be equivalent to an imaginary DC source. The current flowing through the capacitor does not have any high-frequency components, and only the DC component of Ix is concerned.

From formula (1.1), we can see:

Because Udc/2=0 and only the ix DC component is considered, it can be seen from equation (1.2):

According to Figure 1, the capacitance of the two capacitors is equivalent to 2C, and at the same time ix flows through the capacitor to produce a capacitor voltage difference Vd/2, then it is obtained by :

From the differential equation of Vd expressed by formula (1.5), the stable process time constant r of the capacitor voltage difference Vd is:

Among them, Vd0 is the initial value of the pressure difference.

According to formula (1.6), the time constant is determined by the switching function Sd(ξ) and the load impedance Zeq(ξ).

(1) If  , Time constant τ→∞, then -t/τ→0. From the solution of the differential equation, that is, equation (1.6), it is known that the voltage difference Vd of the capacitor will maintain the initial voltage difference Vd0 of the capacitor, which means that the voltage difference of the capacitor cannot be balanced. Obviously, if Sd(ξ)=0 or Re{Zeq(ξ)}=0 will cause this situation, the conclusion is better understood from the physical sense. If Sd(ξ)=0, according to formula (1.8), it is known that the switch tube is not turned on, that is, there is no energy exchange between the DC side and the AC side, and the voltage difference Vd of the capacitor obviously needs to maintain the initial state Vd0 of the voltage difference; if Re{Zeq(ξ)}=0, from the midpoint of the bridge arm, the load properties (including filters) are purely capacitive. Under the action of the switching function Sd(ξ), the voltage of the pure capacitive load is directly switched back and forth between the voltages of the two capacitors according to the switching function Sd(ξ), without any influence on the voltage difference of the capacitors. That is, the voltage difference of the capacitor maintains the initial state Vd0 of the voltage difference of the capacitor.

St=(S1S2)-(S1cS2c),   Sd=(S1S2)+(S1cS2c)        (1.8)

(2) If  , then the time constant τ→0, then -t/τ→∞, from the formula (1.7), it can be seen that the capacitor voltage difference will become 0 over time, which means that the capacitor voltage difference will be automatically balanced from the initial state Vd0 to 0.

(3) If , then the time constant , that is, the capacitor voltage difference will decay according to Vd=Vd0·e-t/τ, and the capacitor voltage difference will eventually decay to 0 within a limited time.

So far, we have analyzed the time constant of the capacitor voltage change in the time domain, and the self-equalization characteristic of the capacitor voltage will be derived from the perspective of the time domain.

For the PWM modulation strategy, when the generated bridge arm midpoint voltage waveform f(x, Y) is Fourier decomposed, it contains two variables, as follows:

X=ωct=θc,  Yωst=φs                  (1.9)

Equation (1.10) is the two-variable Fourier decomposition, where: the first row represents the DC component, the fundamental wave component and the baseband harmonic, and the frequency of the baseband harmonic component is an integer multiple of the fundamental frequency; the second row represents the carrier harmonic component, whose frequency is an integer multiple of the carrier frequency; the third row represents the carrier sideband spectrum wave components, located on both sides of the carrier harmonic component, and the offset frequency is the fundamental frequency.

Take the open loop operation of the 3L-NPC half-bridge inverter using the SPWM modulation strategy shown in Figure 2 as an example, and define the frequency modulation ratio as N=fs/fo, where fs is the carrier ct frequency and fo is the modulation wave vm frequency. Taking an even number of the frequency modulation ratio N as an example, the Fourier bivariate Fourier decomposition of St and Sd is carried out according to formula (1.10).

First of all, it is known from Figure 3 that St is a half-wave symmetrical odd function, so its two-variable Fourier decomposition does not contain DC components and even harmonics:

Among them, St_0n (m=1, 3, 5…) is the harmonic amplitude of multiple times of the fundamental frequency of St, St_mn (m=1, 2, 3….; n=±1, ±3, ±5…) is the side frequency harmonic amplitude of multiples of the carrier frequency of St.

Sd is an even function with overlapping half waves, so its Fourier decomposition does not contain odd harmonics.

Among them, Sd_dc is the DC component of Sd, Sd_0n(r=2, 4, 6…) is the harmonic amplitude of multiples of the fundamental frequency of Sd, and Sd_mn(m=1, 2, 3, …; m=0, ±2, ±4…) is the central harmonic and its side frequency harmonic amplitudes of multiples of the carrier frequency of Sd.

It can be seen from formula (1.14) that the output voltage uinv of the 3L-NPC bridge arm is composed of two parts: 0 output voltage uinv_b=Udc·St/2 when the capacitor voltage is balanced; ②The output voltage uinv_d=Vd·Sd/2 caused by the capacitor voltage difference Va when the capacitor voltage is unbalanced. The next article analyzes the characteristics of the current ix(t) and its average value Ix(avg) from the midpoint of the capacitor bridge arm when Vd=0 and Vd≠0.