Time domain analysis of capacitor voltage self-balance mechanism Part 2

Time domain analysis of capacitor voltage self-balance mechanism Part 2

This article analyzes the characteristics of the current ix(t) and its average value Ix(avg) from the midpoint of the capacitor arm when Vd=0 and Vd≠0.

(1) Vd=0

Vd=0 means that the capacitor voltage is balanced. At this time, iinv(t) is denoted as iinv_b(t), and its expression is:

Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.1)

Among them, φZmn is the impedance angle of Zeq, and φZmn∈[-π/2,π/2], m=0,1,2,3,…,n=±1,±3,±5…

Time domain analysis of capacitor voltage self-balance mechanism Part 2
Figure 1 – Time domain waveforms and spectrograms of St and Sd
Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.2)

It can be seen from equation (1.1) that iinv_b(t) only contains odd harmonics, while Figure 1 shows that Sd contains only DC components and even harmonics. According to formula (1.2) ix=-iinvSd, the average value Ix(aveg)_b of the current ix(t) out of the midpoint of the capacitor bridge arm is:

Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.3)
Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.4)

From equations (1.3) and (1.4), it can be seen that the average current of capacitors Cdc1 and Cdc2: I1 (avg) = I2 (avg) = 0, which shows that when the capacitor voltage of 3L-NPC is balanced, there are:

① The average value of the current flowing out of the midpoint of the capacitor bridge arm is 0:

② There is no DC component in the capacitor current, and the average value of the capacitor voltage will stabilize at Udc/2;

③Factors such as load nature and capacitance deviation do not affect the equilibrium state of capacitor voltage.

(2) Vd≠0.

Vd≠0 means that the capacitor voltage is not balanced. At this time, iinv(t) is recorded as iinv_b(t), and its expression is rewritten as formula (1.5):

Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.5)

Then the current iinv-nb(t) consists of two parts, iinv-b(t) and iinv-d(t), iinv-b(t) is shown in formula (1.1), iinv-d(t) is:

Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.6)

It can be seen from equation (1.6) that iinv-d(t) contains DC components and even harmonics. It also shows that when the capacitor voltage is unbalanced, the current iinv-nb(t) before filtering contains a DC component, which is recorded as iinv-nb(avg), and its magnitude is:

Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.7)

Therefore, when the capacitor voltage is unbalanced, the average value Ix(avg)_nb of the current ix(t) flowing out of the midpoint of the capacitor bridge arm is:

Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.8)

Combining formula (1.3) with formula (1.6) and the property that the product of different trigonometric functions is zero in one cycle, we can get:

Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.9)

Among them, φZmn is the impedance angle of Zeq, and φZmn∈[-π/2, π/2], m=0, 1, 2, 3., n=0, ±2, ±4….

From the formula (1.9), it can be seen that the magnitude of Ix(avg)_nb is derived from the contribution of the two properties of the bridge arm output current iinv(t), which are the DC component and even harmonic components of iinv(t) respectively, where Kdc and Kharm are respectively:

Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.10)

According to formula (1.9) and formula (1.4), if (Kdc+Kharm)>0, then Ix(avg)_nb is inversely proportional to Vd. This shows that when Vd>0, that is, U1>U2, Ix(avg)_nb<0, then IC1(avg)<0, lC2(avg)>0, the capacitor Cdc1 will discharge and the capacitor Cdc2 will charge until the voltages of the two are equalized; when Vd<0, the same is true. This use of topology and SPWM modulation characteristics to achieve capacitor voltage balance is called self-balance characteristic, of course, this self-balance characteristic is established under the condition of (Kdc+Kharm)>0.

Therefore, it is necessary to discuss the situation of (Kdc+Kharm)>0, that is, what factors determine (Kdc+Kharm)>0. Figure 2 shows the self-balancing characteristics of 3L-NPC and the source of self-balancing current when Zeq is a load of different nature. In Figure 2, iinv(t) is the output current of the inverter bridge arm, which can be seen in combination with equation (1.9). out:

①Except for Zeq which is purely capacitive, the 3L-NPC topology has the characteristics of capacitive voltage self-balancing, and the pure capacitive load condition does not exist, because the actual circuit has a certain parasitic impedance;

②According to the relationship between |Zeq(jω)| and ω according to different load properties, combined with the frequency spectrum of Sd in Figure 1, Sd_dc and Sd_10 (at fs) are larger, then the magnitude of Ix(avg)_nb mainly comes from the DC component of iinv(t) and even harmonic components near the switching frequency;

③Usually, the filter has a greater effect on the attenuation of the switching frequency sub-harmonics, but has no effect on the DC component, so the DC component of iinv(t) is also reflected in the load current io(t), then:

Time domain analysis of capacitor voltage self-balance mechanism Part 2
(1.11)
Time domain analysis of capacitor voltage self-balance mechanism Part 2
Figure 2 – When Zeq is a load of different nature, the self-balancing characteristics of 3L-NPC and the source of self-balancing current

Therefore, the DC component of the load current io(t) is proportional to the capacitor voltage difference Vd.

In summary, under open-loop operating conditions, when the voltage of the 3L-NPC capacitor is unbalanced, except for the case where Zeq is purely capacitive, a DC current opposite to the capacitor voltage difference Vd will be generated in the capacitor current. This current will eliminate the capacitor voltage difference. This characteristic is called self-balancing. The self-balancing current mainly comes from the DC component of the bridge arm output current iinv(t) and even harmonic components near the switching frequency.

In order to fully illustrate the self-balancing characteristics of 3L-NPC, simulations were performed under the conditions that the fundamental impedance of Zeq is approximately purely resistive, resistive-inductive, resistive-capacitive, purely inductive, and purely capacitive. Figure 3 shows the open-loop simulation waveform when Zeq is a purely resistive load. Figure 4 shows the open-loop simulation waveforms when Zeq is of different load properties. It can be seen from Figure 3 and Figure 4 that due to the deviation of the capacitance value, the initial value of the capacitor voltage has a deviation. When Zeq is operating in open loop under pure resistive, inductive and capacitive loads, uC1 keeps decreasing and uC2 keeps increasing until the capacitor voltage is balanced, and the equilibrium state is maintained to work, realizing the self-balance of capacitor voltage. Among them, when Zeq is a purely inductive load, it is easy to cause low-frequency oscillation; when Zeq is purely capacitive, uC1 and uC2 are basically unchanged, and the capacitor voltage cannot be balanced. Fortunately, in actual circuits, purely inductive and purely capacitive loads do not exist.

Time domain analysis of capacitor voltage self-balance mechanism Part 2
Figure 3 – Open loop simulation waveform when the capacitance value is deviated and Zeq is a pure resistive load
Time domain analysis of capacitor voltage self-balance mechanism Part 2
Figure 4 – Open loop simulation waveform when the capacitance value is deviated and Zeq is of different load properties